Modern VLSI systems exhibit increasing complexity. The size of a design not only grows, but the system architecture also becomes more and more heterogeneous and parallel. A key factor for a successful implementation is modeling and simulation of the design. However, modeling at register-transfer level (RTL) is not feasible anymore as a starting point. Already in the concept phase of a design quantitative estimations of the system's performance are required. To effectively support system engineers during this design phase we have developed a performance evaluation framework called SystemQ. By starting with a performance model we show how the system's behavior and structure can be refined systematically. SystemQ is implemented in SystemC and seamlessly supports the refinement of performance models down to transaction level and RTL.