Gesellschaft für Informatik e.V.

Lecture Notes in Informatics


Software Engineering 2013 - Workshopband P-215, 59-74 (2013).

Gesellschaft für Informatik, Bonn
2013


Copyright © Gesellschaft für Informatik, Bonn

Contents

Vice-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors

Dennis Klassen

Abstract


Simulation of processors is needed in early stages of development to reduce cost and increase quality of processor designs. Suitable simulators can be generated automatically from high-level specifications of the processor architecture. For this purpose, we have developed the domain specific visual language ViCE-UPSLA. It allows to describe pipeline based register-register, register-memory processor architectures and generates efficient simulators for such processors. In this way a variety of processors can be quickly prototyped for validation and evaluation. We have successfully used ViCE-UPSLA to model and simulate a processor with an ARM [ARM00] like architecture.


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Gesellschaft für Informatik, Bonn
ISBN 978-3-88579-609-1


Last changed 04.10.2013 18:39:00