### Optimization potential of CMOS power by wire spacing

*P. Zuber*

*, F. H. MÃ¼ller*

*and W. Stechele*

#### Abstract

In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.

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